1. Field of the Invention
Example embodiments relate to a wafer-level stack package and a method of manufacturing a wafer-level stack package. More particularly, example embodiments relate to a wafer-level stack package including semiconductor chips processed at the wafer level and a method of manufacturing the wafer-level stack package.
2. Description of the Related Art
Semiconductor packages are becoming miniaturized and lightweight according to the miniaturization trend of electronic products using semiconductor devices. Examples of the miniaturized and lightweight semiconductor package may include a stack package. In the stack package, stacked semiconductor chips are mounted on a substrate to form one unit semiconductor chip package. Examples of the stack package may include a chip-level stack package and a wafer-level stack package. In the chip-level stack package, a wafer having circuit patterns is cut to form chips and then the chips are stacked and packaged. In the wafer-level stack package, wafers having circuit patterns are stacked and packaged. Accordingly, in the wafer-level stack package, a plurality of chips may be packaged at the same time.
The wafer-level stack package includes a plurality of conductive plugs that penetrate the stacked wafers. The conductive plug connects a circuit wiring of each of the stacked wafers to an external power source.
FIG. 1 is a cross-sectional view illustrating a conventional wafer-level stack package.
Referring to FIG. 1, the conventional wafer-level stack package 1 includes a substrate 10, semiconductor chips 20, an adhesive layer 30, a conductive plug 40 and an external connection terminal 50.
The substrate 10 includes a wiring 12. The semiconductor chips 20 are stacked at the wafer level. The semiconductor chips 20 respectively include pads 22. The conductive plug 40 penetrates the wafers 20 to electrically connect the wiring 12 and the pads 22. The conductive plug 40 penetrates the stacked semiconductor chips 20 to electrically connect a power/ground pad and a signal pad of each of the pads 22 to the wiring 12, respectively. The external connection terminal 50 is provided on a first surface of the substrate 10 opposite to a second surface of the substrate 10 where the semiconductor chips 20 are stacked. The adhesive layer 30 is disposed between the semiconductor chips 20 (wafers) and the substrate 10, as well as between the semiconductor chips 20 (wafers).
The conductive plug 40 has a diameter in the range of several to several tens of micrometers. Therefore, the conductive plug 40 has a relatively low capacitance structure with respect to a signal provided to the signal pad. However, the conductive plug 40 may act as a high inductance path for the power/ground pad. Thus, supply characteristics of a power/ground signal may be deteriorated.